Are you an experienced Hardware Engineering and R&D - Silicon Verification Engineer 2 with a desire to excel? If so, then Talent Software Services may have the job for you! Our client is seeking an experienced Hardware Engineering and R&D - Silicon Verification Engineer 2 to work at their company in Redmond, WA.
Position Summary: The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans.The purpose of this team is IP verification to verify the design of high speed interface connecting different parts of an SOC chip. This role will contribute to internal projects that cannot be shared at the moment. They will be working on Certus interfaces and high-speed serial interfaces (CRDAS) for several projects in AI and compute.
Primary Responsibilities/Accountabilities:
• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
• Support post-silicon verification activities of the products working with design and product teams
• Typical task breakdown and operating rhythm: The role will consist of meetings every day in the mornings which will go over agenda items like tasks and important actions. The remainder of their time is spent heads down focusing on assigned tasks (coding, data analysis, task management).
• Compelling Story & Candidate Value Proposition
• What makes this role interesting? - This role provides the opportunity to work on advanced chips used in AI products.
• Unique Selling Points: The field of AI products is currently expanding; the field is very interesting to work in and support as this role will support the development of chips used for these products.
Qualifications:
• Years of Experience Required: 2+, Ideally 3-6 overall years of experience in the field.
• Degrees or certifications required: Not required but nice to have.
• The ideal resume would contain previous experience with mixed signal exposure (analog and digital), and is fluent with SystemVerilog and UVM having significant design verification experience.
• Minimum 2+years experience with SystemVerilog and UVM.
• Minimum 2+years experience with Mixed Signal Verification.
• Minimum 2+years experience with Design Verification Methodology.
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree nice to have
• 2-4 years of relevant experience required.
Preferred:
• Proficient in using Verilog and VMM/OVM/UVM
• Experience in pre and post silicon verification test flow and automated test benches
• Effective communication, collaboration, and teamwork skills