Responsibilities
• Digital logic design using RTL (Verilog preferred), verification and documentation of detailed design solutions that involve SOC, ROIC or FPGA implementations, ensuring they meet performance, power, and area constraints.
• Collaborating with cross-functional teams for integration and verification, including high speed digital designs that interface to DDR memory systems as well as high speed digital interfaces (1GHz+) and high speed SERDES interfaces (>2 GHz).
• Design high-speed data paths to implement arithmetic functions and signal processing algorithms as needed, as well as complex control state machines.
• Design and development of test benches and quality/test requirements for each design.
• Collaboration with Analog IC designers, Physical Design Engineers, HW PCB designers, Software developers, and Mechanical team members to produce high quality designs.
• Accurately and concisely present design and simulation results to clients, colleagues, designers, and managers.
Requirements
• Bachelors in Electrical Engineering/Computer Engineering or a related field, Masters degree preferred.
• New grad Bachelors and Masters students welcome to apply!
• 1-5 years of related experience a plus.
• Due to government contract requirements candidates must be a US Citizen.
• Understanding of digital logic design and verification principals.
• Proficiency in RTL coding and verification using Verilog/SystemVerilog.
• Knowledge of logic synthesis and timing analysis.
• Knowledge of computer arithmetic, digital signal processing and related VLSI architectures.
• Knowledge of Microsoft Office products including Visio.
• Ability to identify and solve complex design problems and strong analytical and debugging skills.
• Excellent written and verbal communication skills, ability to work effectively in a team environment.
Nice-to-haves
• Video and imaging application experience, including camera or imager design for visible and LiDAR type cameras/applications.
• Additional RTL coding languages - SystemVerilog, VHDL.
• Experience with simulation tools like Mentor Modelsim or Questa, Cadence Xcelium.
• Experience with design for test (DFT) methodologies.
• Understanding of physical implementation, including logic synthesis and experience with Cadence Genus or similar.
• Understanding of STA and experience with Cadence Tempus.
• Experience with Cadence Conformal.
• Some FPGA design experience with Xilinx, Altera, and Lattice.
• Experience with CM tools like Omnify (PLM) and SVN (Rev Control) or similar.
• MATLAB, Python, Perl or other SW language knowledge for scripting and test bench automation.
• Familiar with common test equipment such as oscilloscopes, function generators, VOM, logic analyzers, parametric analyzers, etc.
Benefits
• Competitive benefits package including health insurance, retirement plans, and performance-based compensation programs.