Silicon Design Engineer (Contract)
Please note that this is a contract role providing services to Microsoft through external staffing partners of Allegis Global Solutions. If you are selected for this role, you will be employed by AGS and will not be an employee of Microsoft.
Summary
The main function of a Silicon Design Engineer is responsible of all design tasks at the block and sub-system levels. These tasks include RTL design, integration, LINT, CDC, RDC, Synthesis.
Job Responsibilities
• Responsible for various design tasks at the block level.
• Responsible for various design tasks at the sub-system level.
• Assist in the design flow development/automation.
• Assist in the infrastructure and toolchain.
Requirements
• 10+ years of relevant experience required.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related degree.
• Expertise in Verilog or System Verilog Design.
• Experience in Spyglass LINT, RDC and any CDC tool.
• Experience with Synthesis (Fuse Compiler preferred) and LEC.
• Experience with GIT and a scripting language.
• Attention to detail; analytical and problem-solving ability.
Additional Details
• Location: Remote
• Duration: 2 Months
• Pay Range: $48 - 54.50 per hour
• Weekly Schedule: 40 hours
AGS is an Equal Opportunity/Affirmative Action Employer (M/F/Disability/Veterans). We will consider all applications without regard to race, gender, sexual orientation, gender identity, age, color, religion, national origin, veteran status, disability, genetic information or any other status protected by applicable law.