Contract Type:
Contract
Specialization:
ASIC Flow
Sub-Specialty:
Front-End
Date Published:
18-Apr-2025
Location: Remote
End Date: 12/31
Typical Day in the Role
Purpose of the Team: The purpose of this team is to build security IP for Microsoft and so we find custom circuits for Implementing the hardware that secures microchips
Key projects: This this role specifically is when we have a subsystem that we get that we build, which is like a root of trust subsystem. This person basically helps with that process of integration. And then there are several different design tools that you have to run in order to make sure that the design is in good shape and good to release into silicon. We're looking for is is just a proficient design integration person who can assist our design lead in assembling and closing out this subsystem for a chip project.
Typical task breakdown and operating rhythm: The role will consist of heads down highly technical work
Compelling Story & Candidate Value Proposition
What makes this role interesting? - This role provides the opportunity to work hands on in the system integration.
Candidate Requirements
Years of Experience Required : 10 overall years of experience in the field.
Degrees or certifications required: NO degree is required to be eligible for this role.
Disqualifiers: Candidates without 10 years of hands-on DOING will not be eligible for the role. Engineers who focus on physical design would not be a fit. No analog design work.
Best vs. Average: Hands-on experience, meets all hard skill requirements. MSFT experience nice to have. This is a position for a front end design person. This is HIGHLY technical work. They need to ideally have done Subsystem design in custom microchips.
Performance Indicators: Performance will be assessed based on how they meet deadlines and quality of work, team feedback.
Top 3 Hard Skills Required + Years of Experience
1. Minimum 10 years Expertise in Verilog or System Verilog Design
2. Minimum 10 years Experience in Spyglass LINT, and any CDC tool.
3. Minimum 10 years experience with Experience in RDC.
Summary:
The main function of a Silicon Design Engineer is responsible of all design tasks at the block and sub-system levels. These tasks include RTL design, integration, LINT, CDC, RDC, Synthesis.
Job Responsibilities:
• Responsible for various design tasks at the block level
• Responsible for various design tasks at the sub-system level
• Assist in the design flow development/automation
• Assist in the infrastructure and toolchain
Skills:
• Expertise in Verilog or System Verilog Design
• Experience in Spyglass LINT, RDC and any CDC tool.
• Experience with Synthesis (Fuse Compiler preferred) and LEC
• Experience with GIT and a scripting language.
• Attention to detail; analytical and problem-solving ability
Education/Experience:
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related degree
• 10+ years of relevant experience required.
Hard Skills Assessments
Expected Dates that Hard Skills Assessments will be scheduled: ASAP.
Hard Skills Assessment Process: The assessment process will include HSA With the sponsor.
Required Candidate Preparation: N/A