Description
We are seeking a Senior ASIC/VLSI Synthesis and Design Engineer to lead the development of high-performance, low-power digital designs for state-of-the-art ASICs and SoCs. This role focuses on optimizing power, performance, and area while ensuring timing closure, gate-level simulation, and post-silicon validation. You will collaborate with cross-functional teams to implement synthesis methodologies, develop constraints, integrate DFT, and conduct power analysis.
Company Culture and Environment
Our company fosters a collaborative and innovative environment where teamwork and cross-functional communication are valued. Engineers are encouraged to bring forward ideas and improvements, contributing to a culture of continuous enhancement in design methodologies.
Career Growth and Development Opportunities
The position offers ample opportunities for professional development and career advancement within a cutting-edge technological landscape. You will gain exposure to industry-standard EDA tools and methodologies, promoting skill enhancement and career progression.
Detailed Benefits and Perks
• Competitive total compensation package including base salary, bonus, and equity
• Comprehensive health, dental, and vision insurance
• Opportunities for continuous learning and professional development
• Flexible working hours and remote work options available
Compensation and Benefits
• Competitive base salary
• Performance-based bonus
• Equity options
• Comprehensive health benefits
Why you should apply for this position today
Joining our team provides a unique opportunity to work on cutting-edge technology in the ASIC and SoC domain. You will impact the development of high-performance designs while collaborating with a talented group of engineers, enhancing both your skills and career trajectory.
Skills
• Expertise in ASIC/VLSI design with a focus on synthesis and timing closure
• Proficiency in Verilog/SystemVerilog RTL coding
• Experience with synthesis tools from leading EDA vendors
• Strong gate-level simulation and static timing analysis skills
• Knowledge of power-aware synthesis techniques
• Excellent post-silicon debug capabilities
• Scripting proficiency
• Strong problem-solving and collaboration skills
Responsibilities
• Develop and implement synthesis flows using industry-standard EDA tools
• Define synthesis constraints and optimize clock distribution and pipelining
• Perform Logical Equivalency Checks and integrate scan chains
• Conduct power analysis and optimization
• Debug timing, power, and area issues
• Collaborate with physical design teams
• Lead design methodology improvements
• Drive post-silicon validation and debug processes
Qualifications
• Bachelor’s degree with 8+ years of experience or Master’s degree with 6+ years in a related technical field
• Expertise in ASIC/VLSI design focusing on synthesis and timing closure
• Proven experience with EDA tools and design methodologies
Education Requirements
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field
• Master’s degree preferred but not required
Education Requirements Credential Category
• Bachelor’s or Master’s degree in a relevant technical field
Experience Requirements
• 8+ years of relevant experience in ASIC/VLSI design for Bachelor’s degree holders
• 6+ years of relevant experience for Master’s degree holders
• Proven track record in synthesis, timing closure, and post-silicon validation
Why work in Tustin, CA
Tustin, CA, offers a prime location with a vibrant community and excellent quality of life. With its close proximity to major tech hubs and beautiful Southern California weather, Tustin provides an ideal environment for both personal and professional growth.