Graduate - IC Verification Engineer

About the position

Responsibilities
• Drive the verification of mixed signal ICs using best practices to achieve first pass silicon success
• Create and verify block level models (system Verilog, VAMS, etc.) for utilization in top level mixed mode simulations
• Develop application specific test benches with automated checkers to assess overall IC functionality and robustness
• Collaborate with application, analog design and digital design leads to understand and verify system level and IC level functions and specifications
• Partner with design team and provide initial analysis of errors found during the verification process
• Foster a speak-up culture of collaboration, innovation, and resilience within the verification team

Requirements
• B.S or M.S. in Electrical Engineering or equivalent
• Studied analog design or mixed signal design verification
• Experience in UVM based design verification
• Experience in modeling analog mixed-signal blocks such as bandgap, oscillators, ADC, DAC, LDOs, gate drivers, and others
• Knowledge of system verilog, VAMS or real number modeling
• Experience writing checkers and assertions for top level parametric assessment and functional coverage
• Knowledge using common EDA tools such as Cadence Virtuoso, Maestro, vManager, and others
• Ability to drive a break the part mentality
• Ability to persevere until all unexpected observations are driven to root cause and closure
• Outstanding communication and leadership skills
• Must be a team player and self-starter
• US citizen or green card holder