MUST BE A US CITIZEN (ITAR REQUIREMENT).
Support a Fortune 500 Aero Defense company as an FPGA/ASIC Design Engineer.
You must have an active United States Department of Defense security clearance to be considered.
The FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, verification/validation through Software integration test, for delivery of complex FPGAs AND/OR ASICs systems. This is a key, high impact, high visibility role in the organization to ensure robust quality and delivery of Communication products for National Security.
Develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high-speed protocols NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs.
Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
The company has deployed state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS).
Skills/Experience:
The successful candidate(s) will possess:
At least 3 year experience with proven track record of implementing complex algorithms targeting ASIC/FPGAs
Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred.
Proficiency in VHDL and FPGA design/debug Xilinx FPGA / Vivado
Excellent Analytical/Debug skills
Good verbal, written, and presentation skills
US Citizenship required
Required Skills:
VHDL Experience is required for all candidates to be considered.
1. Looking for mid-senior level folks
2. Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
3. Must have done hands on multiple complex designs arch / design / verification / Synthesis / STA
4. Big Plus
a. Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
b. Mentor EDA CDC/Lint/AC/RDC