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Summary
We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and integrate advanced IP and AI accelerators into SOC/ASIC solutions to enable in-system testing and prototyping. The goal is to de-risk new IP/accelerators, prove out advanced compute/memory architectures and to harden controls/algorithms for next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a key contributor in planning and executing our front-end and back-end digital design efforts at the IP and sub-system levels. From microarchitecture definition and RTL implementation to synthesis and timing closure, fundamentals in digital design will enable you to contribute to all phases of the chip development. Additionally, effective collaboration and communication with Digital Design Engineers, Digital Verification Engineers, Research Scientists and XFN teams will be key to your success.
Required Skills
Digital Design Engineer, Reality Labs Silicon AI Research Responsibilities:
• Contribute to microarchitectural feature definition, RTL design, design verification and project planning
• Deliver quality RTL in collaboration with Digital Verification (DV)
• Support back end physical design (PD) through STA and SDCs
• Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads
• Help create and maintain design documentation including IP/SoC Micro Architecture document (collaborator/owner), IP/SoC Design plan (collaborator) and SoC/chip bringup/validation plan (collaborator)
Minimum Qualifications
Minimum Qualifications:
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 3+ years of experience as a Digital Design Engineer
• Communication and collaboration skills
• Knowledge of digital SoC integration and ASIC architecture
• Skilled in micro-architecture, RTL coding, design verification and SoC Integration of complex IPs
• Experience in CDC, SDC and STA
• Self directed and detail oriented in all phases of digital design
Preferred Qualifications
Preferred Qualifications:
• Python (or similar) scripting experience
• Familiarity with low-power design techniques
• Knowledge of common industry interfaces like AXI, APB, I3C, SPI, UART, etc
• Experience using C for system verification
• Experience in DFT/Testability requirement definition and understanding of test program development
• Familiar with IP, sub-system and SoC DV to execute DV working with DV lead
• Some familiarity with compute and/or memory architectures for ultra low power applications
• Master's degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience
Public Compensation
$142,000/year to $203,000/year + bonus + equity + benefits
Industry: Internet
Equal Opportunity
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.