About the Company: We are a leading semiconductor design company committed to innovation and excellence in technology. Our mission is to deliver cutting-edge solutions that empower our clients and enhance their capabilities. We foster a collaborative and inclusive culture that values diversity and encourages professional growth.
About the Role: We are seeking an experienced Design-for-Test (DFT) Engineer to join our semiconductor design team in Austin, Texas. You will be fully responsible for implementing advanced DFT methodologies for next-generation SoCs and work closely with digital, analog, VLSI, and verification teams. This role offers H1B sponsorship for the right candidate.
Responsibilities:
• Define and implement SoC DFT strategies & architecture (ATPG/DFT/MBIST)
• Insert and debug scan chains, boundary scan, compression, Logic BIST, TAP controller
• Integrate & verify MBIST logic & memory test controllers
• Perform DFT rule checks, fault modeling, and debug ATPG patterns
• Support silicon bring-up and validation on ATE
• Collaborate with VLSI, backend, and analog teams to ensure high test quality
• Document DFT methodology and test processes
Qualifications:
• 5+ years of hands-on DFT experience in ASIC / SoC designs
• Experience in DFT architecture, insertion, ATPG, MBIST, JTAG
• Hands-on with ATE debugging, compressed patterns, and silicon bring-up
• Fault modeling & DFT verification experience
Preferred Skills:
• Master’s in Electrical Engineering or related field
• Experience with EDA tools: Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, TestKompress
• Experience in IP integration (Memories, TAP, MBIST)
• Knowledge of ASIC synthesis, simulation, and hierarchical design flows
Pay range and compensation package: Competitive salary based on experience and qualifications.
Equal Opportunity Statement: We are an equal opportunity employer and are committed to creating a diverse and inclusive workplace. We welcome applicants from all backgrounds and experiences.