ASIC/RTL/SOC Design Engineer
Wipro
Full-time
On-site
Job Title: ASIC/RTL/SOC Design Engineer
Duration: Full Time
Location: Sunnyvale, CA
Description :
• Logic design /micro-architecture / RTL coding is a must.
• Expertise in Verilog & System Verilog is a must.
• Experience in Synthesis / Understanding of timing concepts for ASIC is required.
• Static checking tools like Lint, CDC, RDC, Spyglass DFT etc experience required.
• Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus.
• Hands on experience in Multi Clock designs, Asynchronous interface is a must.
• Knowledge of low power concepts and experience is a plus.
Duration: Full Time
Location: Sunnyvale, CA
Description :
• Logic design /micro-architecture / RTL coding is a must.
• Expertise in Verilog & System Verilog is a must.
• Experience in Synthesis / Understanding of timing concepts for ASIC is required.
• Static checking tools like Lint, CDC, RDC, Spyglass DFT etc experience required.
• Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus.
• Hands on experience in Multi Clock designs, Asynchronous interface is a must.
• Knowledge of low power concepts and experience is a plus.