Minimum qualifications:
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 3 years of experience in ASIC design or equivalent practical experience.
• Experience in chip power analysis.
• Experience in scripting languages such as Python.
Preferred qualifications:
• Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
• Experience performing chip power analysis using EDA tools such as PTPX, PowerArtist, or PrimePower.
• Experience driving power-efficiency improvement in chip designs.
• Experience with pre-silicon vs post-silicon power correlation.
• Experience in building or maintaining automated tool flows.
• Proficiency in RTL languages such as SystemVerilog.
About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of the TPU Power Design team, you will play a pivotal part in the power architecture and microarchitecture for our TPUs. This highly cross-functional role spans pre-silicon power modeling, to design methodology, to post-silicon data collection and analysis. Starting off by driving design power analysis, you will grow into helping define design and methodology improvements to achieve more power efficient designs. You will possess a solid understanding of power fundamentals and silicon design concepts, some exposure in performing chip power rollups, and also have an affinity for diving into adjacent disciplines in pre and post silicon.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
• Drive power analysis for our silicon designs.
• Develop tests and benchmarks for measuring chip power consumption.
• Develop design improvements to increase power efficiency.
• Collaborate with cross-functional teams in defining power strategy and specifications.
• Define methodology for measuring and rolling up power using EDA tools.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .