The ASIC Design Engineer Intern will join Meta's Infrastructure organization, contributing to the design and verification of advanced IPs for data center accelerators. This role offers the opportunity to work alongside expert ASIC engineers, focusing on enhancing the efficiency of data centers through innovative design practices.
Responsibilities
• Participate in Micro-architecture, Design, and Verification reviews and provide feedback
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• Design and develop RTL or HLS code for some of the IPs
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• Analyze designs and enhance PPA (Power, Performance, Area)
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• Support and develop Verification Infrastructure, analyze and improve Verification Coverage
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• Support Simulation accelerators and post-Silicon validation
Requirements
• Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
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• Knowledge of Verilog or System Verilog or HLS
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• Knowledge of Computer Architecture and Logic Design fundamentals
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• Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
Nice-to-haves
• Currently has, or is in the process of obtaining, a Masters or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields
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• Experience with Lint, Synthesis, Formal or Physical Design tools
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• Scripting capability with Python or Perl
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• Experience with High Performance Computing
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• Experience with Digital Signal Processing Techniques
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• Creativity and problem solving capabilities
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• Intent to return to degree-program after the completion of the internship/co-op
Benefits
• $6,375/month to $11,067/month compensation
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• Health insurance
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• Paid holidays
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• Professional development opportunities