Minimum Requirements: (“Must have” Qualifications) At least 4 years of experience with pre-silicon DV (Design Verification)
Must have hands-on experience with writing code using System Verilog and UVM over the past 2 years
Must be a quick learner, independent and communicate well.
Knowledge and hands-on experience with Verilog, System Verilog, UVM, debugging waveforms
Must be proficient with:
Building a testbench for a medium complexity block using System Verilog and UVM
Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM
Developing, maintaining and supporting the UVM verification environment
Debugging tests with design engineers to deliver functionally correct design blocks
OOPS, randomization, constraints, interfaces
Writing & analyzing functional coverage, assertions
Generating and analyzing code coverage & writing waivers
Desired Skills/Qualifications/System Experience requirements: (“Nice to have Qualifications”) Experience with verification of networking products and networking background
Experience with DMA based verification
Qualified candidates should send their resume and application to: hr@ptecsolutions.com
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